Plasma display panels, or gas discharge panels, are well known in the art and, in general, comprise a pair of transparent substrates respectively supporting column and row electrodes, each coated with a dielectric layer and disposed in parallel spaced relation to define a gap therebetween in which an ionizable gas is sealed. The substrates are arranged such that the electrodes are disposed in orthogonal relation to one another thereby defining points of intersection which in turn define discharge cells at which selective discharges may be established to provide a desired storage or display function. It is also known to operate such panels with AC voltages and particularly to provide a write voltage which exceeds the firing voltage at a given discharge point, as defined by a selected column and row electrode, thereby to produce a discharge at a selected cell. The discharge at the selected cell can be continuously "sustained" by applying an alternating sustain voltage (which, by itself is insufficient to initiate a discharge). This technique relies upon the wall charges which are generated on the dielectric layers of the substrates which, in conjunction with the sustain voltage, operate to maintain discharges.
Details of the structure and operation of such gas discharge panels or plasma displays are set forth in U.S. Pat. No. 3,559,190 issued Jan. 26, 1971 to Donald L. Bitzer, et al.
AC plasma displays have found widespread use due to their excellent optical qualities and flat panel characteristics. These qualities have made plasma displays a leader in the flat-panel display market. However, plasma panels have gained only a small portion of their potential market because of competition from lower cost CRT products.
Various attempts have been made to reduce the costs inherent in AC plasma panel structures. One of the more successful is described in U.S. Pat. No. 4,772,884 and is entitled "Independent Sustain and Address Plasma Display Panel", by Weber et al. (one of the inventors hereof). That patent describes an electrode geometry change from the standard AC plasma technology wherein the address and sustain functions are carried out on separate panel electrode structures. Separating those two functions has enabled implementation of both a different addressing scheme and provided reductions, by a factor of two, in the number of required address drivers (as compared to the number required for the standard AC plasma technology). Furthermore, the address drivers did not have to supply sustain currents and could be made much smaller and therefore less expensive.
In FIG. 1, an 8.times.8 pixel, independent sustain and address (hereinafter called "ISA") plasma panel schematic is shown. FIG. 2 shows an expanded view of the area in circle 10 in FIG. 1. The expanded view in FIG. 2 shows a basic nine cell group that is the repetitive unit in the ISA geometry. Each of the nine cells is defined in accordance with the types of electrodes that intersect to define a cell. In plasma panels existing prior to the ISA technology, all cells on the panel were electrically identical and, in fact, were all display pixels. However, in an ISA panel, only four of the nine cells of a cell group are display pixels i.e. P1, P2, P3, and P4. Those pixel cells are located at the intersections of four sustain electrodes XSa, XSb, YSa, and YSb. In addition to the four pixel cells, there are five other cells in a cell group. At the center of the cell group is an address cell A which occurs at the intersection of two address electrodes XA and YA. There are also four coupling cells: C1, C2, C3, and C4 which occur at the intersections of a sustain electrode and an address electrode. The coupling cells are divided into two groups depending upon their position relative to the address cell. The C1 and C4 cells are called vertical coupling cells and the C2 and C3 cells are called horizontal coupling cells. It should be understood, that the terms vertical and horizontal are used merely to designate orthogonal orientations of conductors and cells and for easy reference purposes.
All horizontal electrodes of the ISA panel reside on one substrate of a panel and are referred to as the Y electrodes. All vertical electrodes reside on an opposite substrate and are termed X electrodes. As is well known, between the substrates, an ionizable gas is positioned and provides the selected cell illumination. The X address electrodes comprise electrodes 12, 14, 16 and 18 whereas the Y electrodes comprise 20, 22, 24, and 26. Each X electrode can be selectively addressed by a column address and driver circuit 28 and each Y address line can be addressed by a row address driver circuit 30.
X sustain signals are provided by two, phased, sustain generators 32 and 34, with each of the aforementioned sustain generators coupled to a connected pair of parallel sustain lines (e.g. 36, 38). Each pair of sustain lines, e.g. 36, 38, is shorted together by shorting bars at either end, thus forming a sustain electrode pair. Alternating sustain electrode pairs on a given substrate are bussed together by a sustain bus and are connected to one of the two sustain drivers. Row sustain drivers 40 and 42 are similarly connected to interspersed row sustain pairs.
In FIG. 3, waveforms are shown which describe a basic cycle for an ISA plasma panel as described in the aforementioned U.S. Pat. No. 4,772,884. In a preferred mode of operation, two rows of pixel cells are initially turned on. Then, an erase cycle is performed to selectively turn off pixels which the image data indicate should be in the off state. The waveforms of FIG. 3 assume that a "write two rows" cycle has already occurred. The selective erase of certain desired "on" pixels encompasses two steps. The first step causes a discharge to occur in selected address cells along a selected YA address electrode (see FIG. 2). This results in the migration of wall charges into vertical coupling cells C1 and C4.
This is described in more detail by the waveform diagram of FIG. 3. Prior to the selective erase occurring, reset pulses are applied to the X and Y address lines to reset the wall voltages in vertical coupling cells C1 and C4. The simultaneous application of sustain voltages to XSa, XSb and YSa, YSb sustain lines with the reset pulses will cause small discharges to occur in the coupling cells which serve to adjust their wall voltages.
Subsequently, erase address pulses 50 and 52 are applied to the XA and YA address lines respectively. This commences Step 1 of the selective erase procedure and its effect is shown in FIG. 4. The erase address waveforms are polarized so that the XA and YA electrodes are the anode and cathode respectively. Since the XA electrode is the anode, the plasma discharge 54, which occurs at address cell A, spreads predominantly towards vertical coupling cells C1 and C4. The voltage across the gaps in each of coupling cells C1 and C4 is such that the spreading plasma deposits significant negative charge into these cells. In FIG. 5, a sectional illustration taken along line 5--5 in FIG. 4 (Step 1) is shown and illustrates the plasma spreading activity during Step 1 and the charges on the inner walls that are present at coupling cells C1 and C4 and address cell A.
Step 2 of the selective erase address performs two degrees of selection. It commences at the fall of erase address pulses 50 and 52 and the rise of certain selection potentials on the sustain electrodes. As shown in FIG. 5, Step 1 deposited equal amounts of wall charge into coupling cells C1 and C4 when address cell A was discharged. By raising only a Y sustain line associated with a selected vertical coupling cell, the unselected vertical coupling cell, defined by the non-raised Y sustain line, will not discharge.
During Step 2, the selected YS and XS electrodes are the anode and cathode respectively. This polarization enables the plasma generated by the discharge of a coupling cell to spread horizontally away from the cell and into neighboring pixel cells. Sectional views taken along line 6--6 in FIG. 4 (Step 2) are shown in FIGS. 6a-6d and further aid in understanding the operation of the selective erase. In FIG. 3, the waveforms impressed on the X and Y sustain lines during Step 2 enable the selection of which of the pixel cells is to be erased.
In FIG. 6a, it is assumed that Step 1 has already occurred; that coupling cell C1 has substantial wall charges which are polarized to provide a more positive voltage under the YSa electrode; and that both pixel cells P1 and P2 are in the on state. At this point, it is desired to erase the P1 cell while leaving the P2 cell in its on state. Thus, 100 volt potentials are applied to the XSa and YSa electrodes respectively, and zero volts are placed on the XA and XSb electrodes. The stored wall charges in coupling cell C1 add to the applied potential on the YSa electrode to cause a discharge in cell C1. At the same time, there occurs a discharge in cell P2 but none occurs in cell P1 due to the fact that identical voltages exist on its bounding electrodes. The plasma which results from the discharge of cell C1 spreads along the YSa electrode and neutralizes any preexisting wall charges in cell P1, thereby causing it to be erased. Since cell P2 is already discharged, the migration of additional charge states thereinto has no effect.
In FIG. 6c, a different set of initial conditions are assumed. In this case, cell P2 is in the off state and cell P1 is to be erased without affecting the state of cell P2. Since the dielectric immediately beneath the YSa electrode in cell P1 has a positive wall charge, the electrons resulting from a subsequent discharge of coupling cell C1 preferentially migrate thereto and neutralize the preexisting wall charge. Preexisting negative wall charges in pixel cell P2 tend to repel the electrons resulting from the discharge in coupling cell C1 and cell P2 remains unaffected. Thus it can be seen, that the sustain line that is raised during Step 2 of the selective erase, determines the type of pixel cell that will be erased. Therefore, to erase a selected type of pixel cell, the two sustain electrodes that define the selected pixel cell type should rise simultaneously, following the fall of the XA address pulse.
As a consequence of reducing the number of address drivers by a factor of two, the ISA plasma display panel, in its simplest form, is a factor of two slower in updating a given panel size, when compared to a standard AC plasma panel. Since there is only one address driver for each two rows or columns of pixels, the two selective erase cycles delay the overall operation of the panel. This factor becomes a problem when the number of rows of data or the frame update rate is high. If the frame update rate needs to be increased for any reason, the maximum number of rows of data that can be displayed is accordingly decreased. Similarly, if the number of rows of display data is to increase beyond a maximum allowable for a given frame update rate, then the frame update rate must be decreased.
Furthermore, it is to be noted that subsequent to each selective erase cycle, previous ISA AC plasma panels have inserted one or more sustain cycles to stabilize the cell wall charges. Thus, in addition to the time taken to individually erase pixels in each cell group, sustain pulses are interspersed between the erase pulses and add to the overall addressing time. Additionally, the duration of the sustain pulses must be such as to assure the proper discharge of cells which are to remain in the "on" state. All of this, combined, adds significantly to the addressing time of the ISA AC plasma panel.
The above stated speed limitation presents problems. Applications which require the use of a mouse, pointer, or graphics frequently require relatively high frame update rates for continuous information display.
Additionally, the ability to effectively exhibit gray scale images depends, to a great extent, upon the speed the display image can be updated.
Accordingly, it is an object of this invention to provide an ISA AC plasma panel with an improved addressing scheme.
It is another object of this invention to provide an ISA AC plasma panel with a substantially increased speed, addressing scheme.
It is still another object of this invention to provide an ISA AC plasma panel with an improved addressing scheme which utilizes existing panel structures.
A still further object of this invention is to provide an ISA AC plasma display panel with a power conserving drive scheme.
Yet another object of this invention is to provide an ISA AC plasma panel with a variable brightness feature.